Designers of circuits (i.e., integrated circuits) may use electronic design automation (EDA) tools, a category of computer aided design (CAD) tools, to create a functional circuit design, including a register transfer logic (RTL) representation of the functional circuit design, synthesize a “netlist” from the RTL representation, and implement a layout from the netlists. Synthesis of the netlist and implementation of the layout involve simulating the operation of the circuit and determining where cells should be placed and where interconnects that couple the cells together should be routed. EDA tools allow designers to construct a circuit, simulate its performance, estimate its power consumption and area and predict its yield using a computer and without requiring the costly and lengthy process of fabrication. EDA tools are indispensable for designing modern integrated circuits, particularly very-large-scale integrated circuits (VSLICs). For this reason, EDA tools are in wide use.
Multiple EDA tools may be used when designing an integrated circuit. To manage the combination of the EDA tools that are used to design an integrated circuit, design flows are typically used. One type of design flow supports a hierarchical design methodology that allows designers to address problems on the physical side of the design process between logic synthesis and the implementation process. In a hierarchical design flow, designers can apply physical constraints to assist in controlling the initial implementations of an integrated circuit design through early analysis and floor planning. Floor planning involves planning for the placement of various components, such as hierarchical design components, inside an integrated circuit. With a hierarchical design flow, EDA tools can allow a designer to reduce the number of iterations between running PAR (Place and Route) and then returning to the register transfer level (RTL) and synthesis thereof.
For a hierarchical design methodology, each functional block of an integrated circuit design is typically characterized into an abstract timing model. The abstracted timing model is employed to in a design flow of the integrated circuit that is used to arrive at timing closure. Different CAD tools are provided that use various abstraction methods to capture the hierarchical modeling information. Extracted Timing Models (ETMs) and Interface Logic Models (ILMs) from Synopsis, Inc., of Mountain View, Calif., are examples of conventional abstraction tools that may be used.
Current design methodologies approach timing model abstraction of hierarchical hard-macros (HHMs) from an outside-in perspective. A HHM is a logical block in a circuit design that is implemented as a physical hierarchy. Though this is the same perspective used to model standard cells such as flip-flops, there are fundamental problems associated with this approach when applied to HHMs. For example, the typical outside-in approach does not consider the fact that models of HHMs interact with CAD tools in a more complex manner as opposed to standard cell models. The models of HHMs are subject to effects of variability in the design flow due to the lack of (and changing nature of) interface information early in the design process. The netlist and parasitics in the early iterations of the block provide an inaccurate representation of the true timing bounds on the interface of the HHMs models, thereby introducing error in the design flow.
Additionally, representing the combinations of the different timing modes for an integrated circuit block, typically referred to as horizontal requirements, and the Process, Voltage and Temperature (PVT) corners for each of the timing modes can be challenging. FIG. 5 provides an example of a conventional hierarchical design flow 500 for designing an integrated circuit that includes X horizontal modes and Y PVT corners for each of the modes. The number of PVT combinations represented increases even more when considering the additional Z parameters needed to represent the timing information from the vertical requirements of the design flow that are generated one model at a time. The vertical portion of the design flow 500 includes timing information from the placement (i.e., ideal clocks information), clock-tree synthesis (CTS) (i.e., propagated clocks information) and routing (i.e., customized timing, derate and on-chip variation (OCV) information). Accordingly, problems with the design of integrated circuit blocks and the integrated circuit can occur.